Methods for fabricating a photolithographic mask and for fabricating a semiconductor integrated circuit using such a mask

ABSTRACT

Methods are provided for designing a photolithographic mask and for fabricating a semiconductor IC using such a mask. In accordance with one embodiment a method for fabricating a semiconductor IC includes determining a design target for a region within the IC. An initial mask geometry is determined for the region having a mask opening and a mask bias relative to the design target. A sub-resolution edge ring having a predetermined, fixed spacing to an edge of the mask opening is inserted into the mask geometry and a lithographic mask is generated. A material layer is applied overlying a semiconductor substrate upon which the IC is to be fabricated and a layer of photoresist is applied overlying the material layer. The layer of photoresist is exposed through the lithographic mask and is developed. A process step is then performed on the material layer using the layer of photoresist as a mask.

TECHNICAL FIELD

The present invention generally relates to methods for fabricating aphotolithographic mask and for fabricating semiconductor integratedcircuits (ICs) using such a mask, and more particularly relates tophotolithographic masks including a sub-resolution edge ring and tomethods for fabricating semiconductor ICs using such masks.

BACKGROUND

The trend in the semiconductor industry is toward more and morecomplexity on each integrated circuit (IC) produced. The increasedcomplexity results in an increase in the number of devices, transistorsand the like, required to implement the circuits. As the number ofdevices increases there is a demand for smaller feature sizes; that is,smaller lines and smaller spaces between lines.

Extensive use is made of photolithography to transfer images from aphoto mask to the surface of a semiconductor substrate upon which the ICis being fabricated. As the feature size is reduced it becomes moredifficult to reliably reproduce the mask images on the substrate.Reproducing feature sizes in the range of tens of nanometers (nm)requires high numerical aperture (NA) optics and off-axis illumination.Unfortunately such techniques for dealing with small feature sizes canlead to difficulties with reproducing large features. For example, whentrying to reproduce wide, spaced apart lines on a semiconductorsubstrate using optical tools suited for small features, a dip in imageintensity between the lines can result in underexposure and a resistscum. The resist scum, in turn, can result in unacceptable processyield.

Accordingly, it is desirable to provide methods for fabricatingphotolithographic masks that overcome the above-mentioned problems. Inaddition, it is desirable to provide methods for fabricatingsemiconductor integrated circuits at high yields. Furthermore, otherdesirable features and characteristics of the present invention willbecome apparent from the subsequent detailed description and theappended claims, taken in conjunction with the accompanying drawings andthe foregoing technical field and background.

BRIEF SUMMARY

Methods are provided for fabricating a semiconductor IC. In accordancewith one embodiment the method includes determining a design target fora region within the IC. An initial mask geometry is determined for theregion, the region having a mask opening responsive to the designtarget. A sub-resolution edge ring having a predetermined, fixed spacingto an edge of the mask opening is inserted into the mask geometry, amask bias is inserted to adjust the mask opening, and a lithographicmask is generated. A material layer is applied overlying a semiconductorsubstrate upon which the IC is to be fabricated and a layer ofphotoresist is applied overlying the material layer. The layer ofphotoresist is exposed through the lithographic mask and is developed. Aprocess step is then performed on the material layer using the layer ofphotoresist as a mask.

In accordance with a further embodiment a method for fabricating asemiconductor IC includes generating a lithographic mask, the maskincluding a transparent region bounded by an opaque region and having atransition region juxtaposed between the transparent region and theopaque region. The transition region has a transmission characteristicbetween transparent and opaque. A layer of material is formed overlyinga semiconductor substrate upon which the IC is to be fabricated and alayer of photoresist is applied overlying the layer of material. Thelayer of photoresist is exposed through the lithographic mask and isdeveloped. A process step is performed on the layer of material usingthe layer of photoresist as a mask.

In accordance with a further embodiment a method is provided forfabricating a photolithographic mask. The method includes determining adesign target for a space between two objects and determining a maskopening necessary for resolving the design target. A fixed spacing froman edge of the mask opening is determined for inserting a sub-resolutionedge ring and a photolithographic mask is generated that includes themask opening and the sub-resolution edge ring.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will hereinafter be described in conjunction withthe following drawing figures, wherein like numerals denote likeelements, and wherein:

FIG. 1 depicts image intensity dip as a function of emission properties;

FIG. 2 illustrates, in cross section a lithographic mask having atransition region;

FIG. 3 illustrates simulation results indicating the effectiveness ofusing the mask of FIG. 2;

FIG. 4 illustrates, in cross section, a lithographic mask having asub-resolution edge ring;

FIG. 5 illustrates simulation results indicating the effectiveness ofusing the mask of FIG. 4;

FIGS. 6-9 illustrate schematically, in top view, a progression of maskgeneration techniques; and

FIGS. 10-13 illustrate, in cross section, method steps for fabricating asemiconductor IC.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and isnot intended to limit the invention or the application and uses of theinvention. Furthermore, there is no intention to be bound by anyexpressed or implied theory presented in the preceding technical field,background, brief summary or the following detailed description.

Photolithographic processing is an important tool in the fabrication ofsemiconductor devices such as semiconductor integrated circuits (ICs).In the photolithographic process a pattern is transferred to a layer ofphotoresist that overlies the surface of a semiconductor wafer byprojecting illumination through a patterned mask so that theillumination exposes portions of the layer of photoresist. If thephotoresist is a positive photoresist the illumination causes a chemicalchange in the illuminated areas making them soluble in a photoresistdeveloper. After applying a developer to the exposed photoresist thetransferred pattern remains on the substrate where it can be used as amask. The mask can be used as an etch mask, ion implantation mask, orthe like in fabricating the semiconductor IC.

The mask used in the photolithography process is a plate of quartz orother transparent material upon which a pattern of opaque shapes isformed. A layer of chrome or other opaque material is deposited on thetransparent plate and then is etched to form the desired shapes. Theshapes formed on the transparent plate are not necessarily identical tothe shapes that are to be transferred to the layer of photoresist. Whenfabricating ICs having very small feature size, for example lines andspaces having dimensions in the tens of nanometers (nm), shapes on themask are distorted when they are projected onto the layer of photoresistbecause of interference, diffraction, reflection, and the like. Theoptical distortions cause variations that are dependent on the density,size and location of nearby features. Some of the distortions resultfrom the optical systems that must be used to resolve the very smallfeatures. These include the use of high numerical aperture equipmentwith the attendant short depth of field and the use of strong off-axisillumination. Several techniques are know and widely used to correct forsome of these distortions. For example, mask bias is used to adjust thesize of an opening on the mask beyond the design target. Sub-resolutionassist features (SRAF) which will be discussed in more detail below canalso be added to a mask pattern. The SRAF acts to improve the depth offocus but is too small for the optics to resolve on the layer ofphotoresist.

One problem that is not addressed by mask bias or by SRAF is that ofimage intensity dip, also known as image sink, encountered in the spacebetween large lines in off-axis illumination. The optics and techniquesnecessary to process small features have an unintended effect on largefeatures. On the typical high density IC many if not most of the deviceson the circuit will be designed with minimum feature size, say 40 nm orless. Some devices in the IC, however, will be designed with largerfeature sizes. For example, adjacent long channel field effecttransistors (FETs) can be designed with gate spacing in the range of 140nm and with a pitch (space plus line width) of 500 nm. FIG. 1illustrates the problem of image intensity dip when processing suchdevices with minimum feature size optics.

FIG. 1 depicts plots of image intensity along vertical axis 20 againstposition on a substrate along horizontal axis 22. The situation depictedillustrates the problem of patterning an opening having a design widthof 140 nm between two wide opaque lines. This could be, for example, thesituation in which two polycrystalline silicon gates are separated by a140 nm opening in an IC having other devices of minimum feature size. Tofabricate an IC having such a gate structure a layer of polycrystallinesilicon is deposited overlying the surface of the semiconductorsubstrate and a layer of positive photoresist is applied overlying thepolycrystalline silicon. Other layers such as an etch stop layer, aplanarizing layer and an antireflective coating (ARC) layer may also beapplied, but those layers are well known in the industry and need not bediscussed in detail. Ideally the layer of photoresist is exposed withillumination (light) passing through a photo mask having an opening of140 nm width. The exposed photoresist is developed and the remainingunexposed photoresist is left as an etch mask to by used to etch theunderlying polycrystalline silicon to form the designed gates. FIG. 1illustrates the simulated image intensity at the photoresist layer forNA=1.35 as a function of sigma, a measure of an emission parameter ofthe incident light. There are a number of lithography simulation toolsavailable, such as ProLith available from KLA-Tencor in San Jose Calif.,that can be used to provide such simulation. Higher values of sigma areneeded for smaller size features. Curve 24 is for a low value of sigma,curve 26 is for a slightly higher sigma, and the value of sigmaincreases monotonically with curves 28, 30, and 32 with curve 32 havingthe greatest value of sigma. The significance of the simulation is thatthere is a dip in image intensity in the center of the space that is tobe removed to form the etch mask. The result of having an imageintensity dip is that the photoresist in the center of the space may notbe adequately exposed, will not be adequately developed, and interfereswith the etching of the polycrystalline silicon. The result may beundesired device source-drain connections, degraded source or draincontacts, or other increased defects that degrade yield of the device.

The left portion of FIG. 2 illustrates, in cross section, a conventionalbinary mask 40 that includes a transparent plate 42 such as a quartzplate and an opaque layer 44, such as a chrome layer, that is patternedto leave a transparent mask opening 46. The transparent mask opening hasa width indicated by double headed arrow 48 that corresponds to thedesign target; that is, the desired space between two lines such as thepolycrystalline gates discussed with respect to FIG. 1. The rightportion of FIG. 2 illustrates schematically, in cross section, a portionof the photolithographic mask as modified in accordance with oneembodiment designed to reduce the image intensity dip illustrated inFIG. 1. First, a partially transmissive material edge ring 52 has beenadded as a transition region at the edges of the mask opening, that is,in relation to the design target. Second, mask bias has been applied tothe mask opening to increase the spacing between opaque regions to awidth indicated by double headed arrow 50. The mask bias may include arule based initial biasing followed by a model based or simulation basedmask biasing. Preferably the partially transmissive material has atransmission with respect to the illuminating radiation of about 50%.The mask thus includes a transparent portion 42, an opaque portion 44,and an edge ring portion 52 having transmission properties betweentransparent and opaque. The optimum width of the mask bias as well asthe optimum width of the partially transmissive material edge ring 52can be determined by modeling using a lithographic modeling tool.

FIG. 3 illustrates simulation results indicating the effectiveness ofusing a partially transmissive material transition edge ring 52 at theedges of the mask opening. Again, image intensity is plotted alongvertical axis 20 and position on a substrate is plotted along horizontalaxis 22. Curve 54 indicates the image intensity dip that is expectedwith a conventional binary mask and curve 56 indicates the imageintensity, without a dip, that can be achieved with a partiallytransmissive transition edge ring 52. Adding a partially transmissivetransition edge ring can substantially eliminate the image intensitydip, but requires a new mask material and mask fabrication process.Fabricating a photolithographic mask having a partially transmissivetransition edge ring requires first using conventional technology todeposit and etch chrome or other opaque material. Then a second layer ofpartially transmissive material must be deposited and patterned to formthe partially transmissive edge ring.

In accordance with another embodiment, as illustrated in FIG. 4, areduction in image intensity dip can be realized with a sub-resolutionedge ring mask 60. The desired reduction in image intensity dip isachieved with this embodiment without the mask fabrication complicationsof adding a partially transmissive material. Mask 60, illustrated incross section and formed on a transparent substrate 62, includes atransparent opening 64 that, in this FIGURE, has already been adjustedfor mask bias and an opaque portion 66. Mask 60 also includes asub-resolution edge ring 68 that is spaced apart from the transparentmask opening by a predetermined spacing indicated by arrows 70. Thespacing of the sub-resolution edge ring from the edge of the maskopening is fixed and does not vary even with adjustments in the maskbias. Sub-resolution edge ring 68 has a width indicated by arrows 72.The edge ring width is small enough that the edge ring issub-resolution; that is, the edge ring cannot be resolved and cannot beprinted on the underlying photoresist layer by the optics employed inexposing the photoresist through the mask. The width of the transparentsub-resolution edge ring preferably is substantially the same as thespacing of the edge ring from the mask opening. The combination of atransparent edge ring separated from the edge of the mask opening by anopaque spacer, each having substantially the same width, provides atransition region that is substantially the same as the partiallytransmissive edge ring illustrated in FIG. 2. Either the partiallytransmissive edge ring 52 or the sub-resolution edge ring 68 serves tosmooth the transition at the edge of the mask opening. Instead of anabrupt transition from fully transparent to fully opaque the edge ringprovides a region of intermediate transmission. Optimum values for theedge ring width and spacing from the mask opening can be determined bysimulation using one of the commercially available lithographysimulation tools.

FIG. 5 illustrates simulation results indicating the effectiveness ofusing a sub-resolution edge ring mask 60 having a sub-resolution edgering 68 spaced apart by a fixed and predetermined distance from theedges of the mask opening. Again, image intensity is plotted alongvertical axis 20 and position on a substrate is plotted along horizontalaxis 22. Curve 80 indicates the image intensity dip that is expectedwith a conventional binary mask and curve 82 indicates the imageintensity, substantially without a dip, that can be achieved with asub-resolution edge ring 68. Curve 80 illustrates the effect that atransparent sub-resolution edge ring having a width of 15 nm spacedapart from the mask opening by a distance of 15 nm has in reducing theimage intensity dip when the space has a width of 140 nm and the linehas a width of 300 nm. The inventors have discovered that asub-resolution edge ring of this width and spacing is effective for arange of line and space widths. For example, an edge ring width/edgering spacing of 15 nm/15 nm is effective for a range of spaces fromabout 120 nm to about 180 nm under the investigated lithographyillumination conditions. The optimal ring width/ring spacing may rangefrom about 15 nm/15 nm to about 30 nm/30 nm depending on the exacttarget line and space dimensions as well as illumination conditions.

As noted, a sub-resolution edge ring of a given width and spacing iseffective for reducing image intensity dip for a range of line widthsand spacing widths. If the IC being fabricated has structures that havewidths that fall outside the range, it may be necessary to use two ormore sub-resolution edge ring widths and spacings. In accordance with anembodiment that addresses that situation, a mask is generated that hasdistinct regions to address the different circuit requirements. Indifferent portions of the mask there are different transparent maskopenings, each bounded by opaque areas. The transparent openings aredetermined by simulation to result in desired design targets. Atransition region, for example a transparent sub-resolution edge ring isinserted in juxtaposition to each of the mask openings. Each transparentsub-resolution edge ring has a width and is spaced from itscorresponding mask opening by an opaque region having a fixed width thatis determined by lithographic simulation to reduce the image intensitydip associated with the width and pitch of the corresponding maskopening.

FIGS. 6-9 illustrate schematically, in top view, a progression of maskgeneration techniques that serve to further illustrate the variousembodiments of the invention. FIG. 6 illustrates a conventional approachto mask fabrication. In mask 88 the shaded portions 90 represent linesto be reproduced on the semiconductor substrate. Region 92, having awidth indicated by double headed arrow 94 is the design target, thedesired spacing between lines 90. Mask biasing is applied to achieve thedesign target and results in a mask opening 96 having a width indicatedby double headed arrow 98. The amount of mask bias is determined bysimulation.

FIG. 7 illustrates an additional conventional approach to maskfabrication in which sub-resolution assist features (SRAF) are employedin a mask 99. SRAF is a well know technique used in mask fabrication andis governed by well know SRAF rules. The mask fabrication begins as inFIG. 6 by defining a design target. SRAF 100 is then inserted inaccordance with the SRAF rules which specify that the sub-resolutionfeatures are positioned at a fixed distance from the design target, forexample at a distance indicated by the double headed arrow 102. Maskdesign continues by applying mask biasing. The amount of mask bias isusually unknown during SRAF insertion, but as illustrated, results in amask opening indicated by double headed arrow 104. As a result of theplacement of the SRAF at a distance from the design target andsubsequent mask biasing, the distance of the SRAF from the edge of themask opening, indicated by arrows 106 is not controlled and is not knownin advance. The unknown spacing of the SRAF from the edge of the maskopening cannot provide a reliable and repeatable smoothing of thetransition from opaque line to transparent space.

In contrast to the placement of the SRAF, the placement of thesub-resolution edge rings in accordance with an embodiment of theinvention is fixed in relation to the edge of the mask opening asillustrated in FIG. 8. In accordance with this embodiment thefabrication of mask 118 begins as in FIG. 6 by defining a design targetfor a region within an IC that is to be fabricated. An initial maskgeometry is determined for the region having a mask opening.Sub-resolution edge rings 120 are then inserted at a predetermined,fixed distance from the edge of the mask opening as determined bylithographic simulation and as indicated by arrows 122. The width of thesub-resolution edge rings are also determined by lithographicsimulation. Following the insertion of the sub-resolution edge rings,mask biasing relative to the design target is applied, causing the maskopening to expand to a width indicated by double headed arrow 124.Despite the mask biasing, the spacing of the sub-resolution edge ring,relative to the edge of the mask opening remains fixed at a distanceindicated by arrows 122. The sub-resolution edge ring is thus able toprovide a transition region juxtaposed between the opaque mask materialand the transparent mask opening. A lithographic mask is generated thatincorporates the sub-resolution edge rings and the mask biasing.

As illustrated in FIG. 9, in accordance with a further embodiment, theuse of sub-resolution edge rings can be combined with SRAF infabricating a photolithographic mask 136. As with the masks illustratedin FIGS. 6-8, the mask fabrication begins by defining a design target94, proceeds with the insertion of SRAF 100 and then the insertion ofsub-resolution edge rings 120 spaced apart from the mask opening by afixed distance 122. The mask design is completed by applying maskbiasing to achieve a mask opening 96 having a width indicated by doubleheaded arrow 140 in the final mask 136. In the final mask thesub-resolution edge rings 120 are spaced apart from the mask opening 96by a fixed distance indicated by arrows 122. The SRAF are spaced apartfrom the design target by a distance indicated by arrows 102 and fromthe mask opening 96 by a distance represented by arrows 106. Thedistance represented by arrows 102 is usually different than thedistance represented by arrows 106 and is not known in advance. Thewidth and spacing of the sub-resolution edge rings, determined bysimulation, achieve a smoothing of the transition from opaque region totransparent region and serve to avoid a substantial dip in imageintensity at the surface of a photoresist layer.

In accordance with one embodiment a rule table is established thatdefines the optimum sub-resolution edge ring width and spacing from anassociated mask opening for a range of initial design target line widthsand line spacings. The rule table is populated by simulating variouscombinations of ring width and spacing. The optimization metrics are thedegree of image intensity dip, edge ring printability, and imagequality. The rule table can also be populated by semiconductorexperiment; that is, using a range of mask options to implement patternsin a layer overlying a semiconductor substrate.

In accordance with another embodiment the step of inserting asub-resolution edge ring into a mask geometry can be done by aniterative process. After determining a design target a width and spacingare selected for a sub-resolution edge ring. Lithographic simulation isapplied to determine a simulated target geometry and the simulatedtarget geometry is compared to the design width. A new width and spacingare selected for the sub-resolution edge ring and the simulation isrepeated. The iterative procedure repeats until the simulated targetgeometry is substantially identical to the design target and the imageintensity dip is minimized. As a further step, mask bias and SRAFplacement can also be included in the iterative process.

In accordance with an embodiment the techniques discussed above,including inserting a transition region, which may be a sub-resolutionedge ring, at the edge of a transparent mask region, are utilized todesign a lithographic mask. The design is then used to generate alithographic mask which is used in the fabrication of a semiconductorintegrated circuit (IC). FIGS. 10-13 illustrate, in cross sectionalviews, methods for fabricating a portion of an IC using such alithographic mask. For purposes of illustration only, but withoutlimitation, the method described will illustrate the fabrication of aMOS IC. The method, of course, can be applied to the fabrication of anytype of IC.

Various steps in the fabrication of semiconductor devices are well knownand so, in the interest of brevity, many conventional steps will only bementioned briefly herein or will be omitted entirely without providingthe well known process details. As illustrated in FIG. 10, the methodbegins by providing a semiconductor substrate 200 upon which the IC 203is to be fabricated. Semiconductor substrate 200 can be silicon or othersemiconductor material commonly used for the fabrication of integratedcircuits. Overlying the semiconductor substrate is a layer of gateinsulator 202 and a layer of polycrystalline silicon 204. A layer ofphotoresist 206, preferably a layer of positive photoresist is appliedoverlying the layer of polycrystalline silicon. Although notillustrated, other layers such as antireflective coatings, etch stoplayers, and the like may also be formed overlying the semiconductorsubstrate.

As illustrated in FIG. 11, a lithographic mask 220 having sub-resolutionedge rings 222 and mask opening 224 designed as described above ispositioned overlying the layer of photoresist. Although lithographicmask 220 is illustrated in spaced apart relationship to photoresistlayer 206, the mask may be in direct contact with the photoresist, ormay be positioned above a projection lens system (not illustrated). Asillustrated by arrows 230, the photoresist layer is exposed toillumination that passes through mask opening 224. The provision ofsub-resolution edge rings 222 avoids a dip in image intensity in thecenter of the mask opening by the illumination striking the photoresistlayer.

The method continues as illustrated in FIG. 12 by developing the exposedphotoresist layer. The exposed portion of the photoresist is soluble ina photoresist developer solution and is removed by the developer. Theunexposed portion 234 of the photoresist is not soluble and remains onthe polycrystalline silicon as a process mask. Because thesub-resolution edge rings prevent a significant dip in image intensityat the center of the mask opening, the photoresist in the center of theopening is fully exposed and can be removed without leaving aphotoresist scum or residue.

The unexposed portion 234 of the photoresist can be used as an etchmask, ion implantation mask, or the like. As illustrated in FIG. 13, theprocess mask is used as an etch mask to etch the polycrystalline siliconto form two spaced apart polycrystalline silicon gate electrodes 240 and242. Lacking any photoresist scum or residue, the polycrystallinesilicon is cleanly etched with out any polycrystalline stringers thatmight decrease yield of the circuit. After etching the exposedphotoresist is removed.

Additional steps, both before and after the method steps illustrated inFIGS. 10-13, of course, as is well known by those of skill in the art,will be taken to complete the IC. Those steps are believed to be wellknown and need not be described here.

While at least one exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations exist. It should also be appreciated that theexemplary embodiments are only examples, and are not intended to limitthe scope, applicability, or configuration of the invention in any way.Rather, the foregoing detailed description will provide those skilled inthe art with a convenient road map for implementing the exemplaryembodiments. It should be understood that various changes can be made inthe function and arrangement of elements without departing from thescope of the invention as set forth in the appended claims and the legalequivalents thereof.

1. A method for fabricating a semiconductor integrated circuit (IC)comprising: determining a design target for a region within the IC;determining an initial mask geometry for the region having a maskopening responsive to the design target; inserting a sub-resolution edgering into the mask geometry, the sub-resolution edge ring having apredetermined, fixed spacing to an edge of the mask opening; inserting amask bias adjusting the mask opening; generating a lithographic mask inresponse to inserting the sub-resolution edge ring and the mask bias;forming a layer of material overlying a semiconductor substrate uponwhich the IC is to be fabricated; applying a layer of photoresistoverlying the layer of material; exposing the layer of photoresistthrough the lithographic mask; developing the layer of photoresist; andperforming a process step on the layer of material using the layer ofphotoresist as a mask.
 2. The method of claim 1 wherein inserting thesub-resolution edge ring comprises inserting a transparent region havinga width substantially equal to the fixed spacing.
 3. The method of claim1 wherein the design target comprises a transparent opening bordered bya pair of opaque stripes and wherein inserting a sub-resolution ringcomprises modeling to reduce image intensity sink in the transparentopening during exposing of the layer of photoresist.
 4. The method ofclaim 3 wherein inserting a sub-resolution edge ring comprisesdetermining, in response to the modeling, a width for the sub-resolutionedge ring and the fixed spacing of the sub-resolution edge ring from theedge of the mask opening.
 5. The method of claim 1 further comprising:determining a rule table of initial mask size as a function of designtarget to determine sub-resolution edge ring width and spacing inresponse to lithographic simulation; and inserting the sub-resolutionedge ring into the mask geometry based on selection from the rule table.6. The method of claim 1 wherein inserting a sub-resolution edge ringcomprises: selecting a sub-resolution edge ring width and spacing andselecting a mask bias; applying lithographic simulation to determine asimulated target geometry; and iteratively repeating until the simulatedtarget geometry is substantially identical to the design target.
 7. Themethod of claim 6 further comprising inserting a standard sub-resolutionassist feature (SRAF) into the mask geometry.
 8. The method of claim 1wherein forming a layer of material comprises depositing a layer ofpolycrystalline silicon and wherein performing a process step comprisesetching the layer of polycrystalline silicon to form a pair of spacedapart MOS gate electrodes.
 9. The method of claim 1 wherein inserting amask bias comprises: determining a mask bias based on a method selectedfrom the group consisting of rule based selection, simulation basedmodeling, and combinations thereof.
 10. A method for fabricating asemiconductor IC comprising: generating a lithographic mask, the maskcomprising a transparent region bounded by an opaque region and having atransition region juxtaposed between the transparent region and theopaque region, the transition region having a transmissioncharacteristic between transparent and opaque; forming a layer ofmaterial overlying a semiconductor substrate upon which the IC is to befabricated; applying a layer of photoresist overlying the layer ofmaterial; exposing the layer of photoresist through the lithographicmask; developing the layer of photoresist; and performing a process stepon the layer of material using the layer of photoresist as a mask. 11.The method of claim 10 wherein generating a lithographic mask comprisesplacing a transition region comprising a partially transmissive materialadjacent the opaque region.
 12. The method of claim 10 whereingenerating a lithographic mask comprises placing a transition regioncomprising a transparent sub-resolution edge ring having a first widthspaced a fixed distance from the transparent region and separated fromthe transparent region by an opaque region.
 13. The method of claim 12wherein generating a lithographic mask comprises generating alithographic mask wherein the transparent region exceeds a design targetby a bias amount determined by lithographic simulation.
 14. The methodof claim 13 wherein generating a lithographic mask further comprisesinserting a sub-resolution assist feature (SRAF) in the opaque regionand spaced apart from the design target by a fixed distance.
 15. Themethod of claim 13 wherein generating a lithographic mask comprises:selecting the first width, the fixed distance, and an initial biasamount; applying lithographic simulation to determine a simulated targetgeometry; and iteratively repeating until the simulated target geometryis within an acceptable range of a desired mask geometry.
 16. The methodof claim 12 wherein placing a transparent sub-resolution edge ringcomprises: determining the first width and the fixed distance bylithographic simulation, the simulation modeling image intensity as afunction of transparent region width and opaque region width with thewidth of the sub-resolution edge ring and the fixed distance of thesub-resolution edge ring from the transparent region as parameters; andselecting a first width and fixed distance in response to a simulationresulting in a minimum dip in image intensity.
 17. The method of claim12 wherein generating a lithographic mask comprises placing atransparent sub-resolution ring having a first width a fixed distanceequal to the first width from the transparent region.
 18. The method ofclaim 12 wherein generating a lithographic mask further comprises, at asecond location on the lithographic mask comprising a second transparentregion bounded by a second opaque region, placing a second transitionregion comprising a second transparent sub-resolution edge ring having athird width separated from the second transparent region by an opaqueregion having a fourth fixed width, the second width and the fourthwidth determined by simulation based on characteristics of the secondtransparent region and the second opaque region, respectively.
 19. Themethod of claim 10 wherein forming a layer of material comprisesdepositing a layer of polycrystalline silicon and wherein performing aprocess step comprises etching the layer of polycrystalline silicon toform a pair of spaced apart MOS gate electrodes.
 20. A method forfabricating a photolithographic mask comprising: determining a designtarget for a space between two objects; determining an initial maskopening responsive to the design target; inserting a sub-resolution edgering at a fixed spacing from the edge of the initial mask opening;applying mask bias to adjust the initial mask opening while maintainingthe fixed spacing; and generating a photolithographic mask comprisingthe initial mask opening, the mask bias, and the sub-resolution edgering.